My curriculum vitae in english, created with the ModernCV template
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\name{Mart\'in}{Ribelotta}
\title{Curr\'iculum Vitae}
\address{Vice Almirante O'Connor 647 5-2}{Bariloche (8400)}
\extrainfo{Birth: March 10 of 1984}
\phone[mobile]{+54~(294)~154~640761}
\email{martinribelotta@gmail.com}
\homepage{www.github.com/martinribelotta}
\photo[64pt][0.4pt]{face.png}
\social[linkedin]{martin-ribelotta}
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\begin{document}
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%\section{Tesis de maestr\'ia}
%\cvitem{t\'itulo}{\emph{T\'itulo}}
%\cvitem{sinodares}{Sinodales}
%\cvitem{descripci\'on}{Una breve descripci\'on de la tesis}
\cventry{2011--2019}{Embedded System Developer}{Emtech S.A.}{Bahia Blanca/Bariloche}{}{
Works made:
\begin{itemize}
\item DSP simulation and testing for radar in VHDL using Questasim/Modelsim
\item Design of acquisition software using Virtex6 FPGA over PCI-express
\item Design and implementation of HDL software for radar simulation over FPGA through PCIe.
\item Design and implementation of HDL, base software, drivers and web application for remote control for acquisition subsystem board based on FPGASoC Zynq7000.
\item Implementation of Softcore LEON3 on Atlys board (Spartan6) (soft core customization, boot, linux embedded, RTEMS and bare metal)
\item RTEMS ports to custom board with Cortex-M4 (serial driver, SPI and I2c).
\item Design and implementation of bridge SPI to AHB.
\item Design and implementation of software and modification of the manufacturer's HDL for high-speed communication on telecommunication board over FPGA Virtex5 and DSP Blackfin over usb.
\item Start-up of Linux systems on ARM9 + FPGA board and implementation of driver for FPGA-SoC bridge.
\item Preliminary routing and revision of the CIAA-NXP board.
\item Schematic port and FPGA + SoC board PCB from OrCad to KiCAD.
\item Design of ad-hoc protocol for LoRa network
\item Design and implementation of IoT communication and control software over RTOS in CorterxM4.
\item Arduino API migration for diferent platforms
\end{itemize}}
\cventry{2009--2011}{Hardware/Software embedded designer and application developer}{EyCON S.A.}{Bahia Blanca}{}
{Works made:
\begin{itemize}
\item Hardware/Software redesign of veicle tracking system.
\item Hardware design, startup and mass-production of Bahia Blanca's RF-id Bus machines.
\item Middleware design of software for data loggin software of Bahia Blanca's RF-id Bus machines.
\end{itemize}}
\cventry{2008}{Junnior Developer}{Ventania Labs.}{Bahia Blanca}{}{High Performance Computing developer.\newline{}%
Works made:%
\begin{itemize}%
\item Startup and maintenance of HPC clusters
\item Image recognition programming in python with OpenCV.
\end{itemize}}
\section{Skills}
\subsection{Programming}
\cvitem{Expertice}{C/C++, Java, Python, VHDL, x86/ARM/RISC-V ASM}
\cvitem{Advance}{Javascript, Tcl, Awk, bash/sh, R(MATLAB), SPARC-ASM}
\cvitem{Mid}{Perl, Ruby, PHP, Verilog/SystemVerilog, C\#, TeX/LaTeX}
\subsection{EDA Tools}
\cvitem{PCB Design}{OrCAD, Altium PCB, KiCAD, Eagle}
\cvitem{HDL/FPGA}{Xilinx ISE, Vivado, LiberoIDE/LiberoSoC, LatticeMicro Diamond, YoSYS/ArachnePNR}
\cvitem{IDEs}{Eclipse, QtCreator, Vim, Matlab, SciLabs, VisualStudio}
\newpage
\subsection{Operating systems}
\cvitem{Linux}{Administration and maintenance of Ubuntu, Debian, Red HAT, SuSe, Slackware and others}
\cvitem{Embedded}{Buildroot, Yocto, Linux From Scratch, OpenWRT, QNX}
\cvitem{RTOS}{FreeRTOS/OpenRTOS, RTEMS, eCos, RTLinux, RTAI, vxWorks, ChibiOS, iTron\&derived, OSEK\&derived, MBED-os}
\subsection{Languages}
\cvitemwithcomment{Spanish}{Native}{Mother tongue}
\cvitemwithcomment{English}{Fluid read/write, Basic conversational}{Autodidact}
\section{Personal Projects}
\subsection{CIAA Project}
\cvlistitem{Actually sub-coordinator}
\cvlistitem{Firmware co-maintainer}
\cvlistitem{PCB Design of CIAA-NXP version}
\cvlistitem{Micropython port maintainer}
\subsection{Personal Projects}
\cvlistitem{Cortex-A9 developer board: \emph{\href{https://github.com/martinribelotta/Board-RZA1L}{@github:Board-RZA1L}}}
\cvlistitem{Embedded-IDE: \emph{\href{https://github.com/martinribelotta/embedded-ide}{@github:embedded-ide}}}
\cvlistitem{Executable loader for embedded devices: \emph{\href{https://github.com/martinribelotta/elfloader}{@github:elfloader}}}
\cvlistitem{ChibiOS javascript interpreter: \emph{\href{https://github.com/martinribelotta/ChibiOS-JS}{@github:ChibiOS-JS}}}
\section{Teaching experience}
\cvlistitem{Cortex-M3 Introduction (UTN FRBB 2011): \emph{\href{https://github.com/martinribelotta/curso\_cm3\_2011}{@github:curso\_cm3\_2011}}}
\cvlistitem{Embedded Linux driver developmen (SASE 2011-2012): \emph{\href{http://www.sase.com.ar/2011/tutoriales/desarrollo-de-driver-para-linux-embebido/}{@SASE2011}}}
\cvlistitem{Sotfware Licences (UTN Avellaneda 2015): \emph{\href{https://github.com/martinribelotta/licence-beamer-es}{@github:licence-beamer-es}}}
\cvlistitem{Micropython over EDU-CIAA. PyCON-AR Bahia Blanca 2016 \emph{\href{https://www.youtube.com/watch?v=pT-AOUzZBsw&t=195s}{mpy-pyconar2016@youtube}}}
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\section{Academic formation}
\cventry{2004--2011}{Ing. Electr\'onico [Electronic Engineer]}{UTN FRBB}{Bah\'ia Blanca}{I have completed 4 over 5 years of bachelor's degree in electronic engineering}{}
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